ECP5 PLL experiments

2020-2-21

I experimented some with the PLL of the ECP5 FPGA and found that if the VCO frequency is much higher than the input frequency (> 100x) then it fails to lock.
The range my ECP5's PLL seems to work at is from 30 to 948 MHz, at 28 MHz the lock is unstable.
In some cases the PLL is unstable but gets stable when I press my finger on top of the FPGA, I guess a ground plane on top of the FPGA could improve stability in real use cases, in case such a PLL configuration would be unavoidable.
If two channels of the PLL are used to generate a frequency, then the formula Fin/(a*d)*b*c applies, where a is the input divider, d the output divider of the channel outputting the signal, b the divider of the channel used for the feedback and c the feedback divider of the PLL.
Further it is possible to select one of the 4 output channels of the FPGA dynamically as an input channel using a mux implemented in the fabric. I tried to use a divider implemented in the fabric as a feedback but it didn't really work and I didn't really finish it. I think duty cycle equalization may be needed (simply using a divide by 2?).
I experimented some with the PLL of the ECP5 FPGA and found that if the VCO frequency is much higher than the input frequency (> 100x) then it fails to lock.
The range my ECP5's PLL seems to work at is from 30 to 948 MHz, at 28 MHz the lock is unstable.
In some cases the PLL is unstable but gets stable when I press my finger on top of the FPGA, I guess a ground plane on top of the FPGA could improve stability in real use cases, in case such a PLL configuration would be unavoidable.
If two channels of the PLL are used to generate a frequency, then the formula Fin/(a*d)*b*c applies, where a is the input divider, d the output divider of the channel outputting the signal, b the divider of the channel used for the feedback and c the feedback divider of the PLL.
Further it is possible to select one of the 4 output channels of the FPGA dynamically as an input channel using a mux implemented in the fabric. I tried to use a divider implemented in the fabric as a feedback but it didn't really work and I didn't really finish it. I think duty cycle equalization may be needed (simply using a divide by 2?).




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